1. Field of the Invention
The present invention relates to semiconductor devices, and a method of manufacturing semiconductor devices. More particularly, the present invention relates to semiconductor devices such as a non-volatile memory device including a floating gate electrode, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Semiconductor memory devices are generally classified as either volatile or non-volatile semiconductor memory devices. Volatile semiconductor memory devices, such as dynamic random access memory (DRAM) devices and/or static random access memory (SRAM) devices, have a relatively high response speed. However, the volatile semiconductor memory devices lose data stored therein when power is shut off. On the other hand, although non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices and/or flash memory devices, have a relatively slow response speed, non-volatile semiconductor memory devices are capable of maintaining data stored therein even when power is shut off.
In EEPROM devices, data may be electrically stored (i.e., programmed) or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism. Flash memory devices are generally classified as a floating gate type or a charge trap type such as silicon oxide nitride oxide semiconductor (SONOS) type devices and/or metal oxide nitride oxide semiconductor (MONOS) type devices.
A floating gate type non-volatile memory device comprises a gate structure and source/drain regions. The gate structure comprises a tunnel insulating layer pattern, a floating gate electrode, a blocking layer and a control gate electrode. A silicon oxide layer formed by a thermal oxidation process may be used as the tunnel insulating layer pattern. A dielectric layer having a multilayered structure, which includes a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer, may be used as the blocking layer. The floating gate electrode and the control gate electrode may include polysilicon doped with impurities.
The tunnel insulating layer is formed on an active region of a semiconductor substrate. The active region is defined by field insulating patterns formed in surface portions of the semiconductor substrate. The blocking layer is formed on the floating gate electrode and the field insulating patterns. The control gate electrode extends in a direction substantially perpendicular to an extension direction of the active region on the blocking layer.
To improve a coupling ratio of the non-volatile memory device, i.e., a ratio of a capacitance (Ctun) of the tunnel insulating layer to a sum the capacitance (Ctun) and a capacitance (Cono) of the blocking layer, a height of upper surfaces of the field insulating patterns may be reduced. However, with such an approach for improving the coupling ratio, although the coupling ratio may be improved, electrical disturbance may occur between the active region and the control gate electrode, thereby deteriorating device reliability.